1. Field of the Invention
The present invention relates to a nitride semiconductor light emitting device such as light emitting diode (LED), laser diode (LD) or the like that operates in the visible to ultraviolet wavelength region, and a method of manufacturing the same.
2. Description of the Related Arts
Nitride semiconductors represented by gallium nitride (GaN) have been used as a material for light emitting elements capable of generating a light in the edge to ultraviolet region. In general, a light emitting element using a nitride semiconductor is provided with a light emitting layer (typically known as an active layer) having a multiple quantum well structure, and p-type and n-type nitride semiconductor layers for current feeding that are disposed above and below the light emitting layer.
With recent advances in the development of GaN substrate, laser diodes now demonstrate high performance of laser, high quality and high yield, which have been made possible by epitaxially growing a n-type nitride semiconductor layer, a light emitting layer, and a p-type nitride semiconductor layer sequentially on a n-type conductive GaN substrate such that dislocation density or defects within an epilayer can be reduced compared with epitaxial growth on a conventional sapphire substrate and the cleaved end-face of a flat resonator can easily be formed.
Moreover, the introduction of an n-type GaN substrate has shorten the manufacturing process of laser diodes by bringing a change in the structure of them, i.e., forming an n-type ohmic electrode on the rear side of the n-type GaN substrate, not on the exposed surface of an n-type nitride semiconductor layer provided to the core of an epitaxial growth layer by the conventional semiconductor process.
As an example, Japanese Patent Application Publication No. 07-45867 disclosed the primary use of Ti/Al electrode as an ohmic electrode at the bottom of an n-type nitride semiconductor, and explained that desirable ohmic contact with an n-type layer could be obtained by annealing the adhered electrode at high temperature.
However, when an electrode having Al on the uppermost surface undergoes annealing at high temperature, Al is oxidized. Thus, in the mount process for a device, if the electrode having Al on the outermost surface was used, bonding by Au wire or Au-based (e.g., Au—Sn alloy) soldering was not so strong but easily separated. As a result, sufficient junction strength between both sides was hard to obtain.
To resolve the above problem, Japanese Patent Application Publication No. 2006-59933 disclosed an ohmic electrode to be formed on the surface of an n-type nitride semiconductor, the ohmic electrode being provided with, from the near side of the n-type nitride semiconductor, a first layer with thickness of 10 to 70 nm including Al and/or an Al alloy, a second layer with thickness of 10 to 300 nm including one or more metals selected from Pd, Ti, Nb, Mo and W for example, which have higher melting point than that of the first layer (Al, Al alloy) and the third layer (Au), and a third layer with thickness of 100 to 1000 nm including Au, in sequential order. The ohmic electrode was then subjected to annealing at 350 to 600° C. to obtain desirable ohmic property to the n-type nitride semiconductor as well as a smooth and lustrous surface and desirable wire bonding property.
In particular, according to Japanese Patent Application Publication No. 2006-59933, it is important that Pd with thickness of 50 nm is used as metal for the second layer, the ohmic property is checked on using, as a parameter, the thickness of a metal film containing Al of the first layer as a main ingredient, and the first layer film thickness is limited to a range of 10 nm to 70 nm so as to reduce contact resistance.
Further, it described that the relationship between the film thickness of the first layer metal and the contact resistance remained the same when the second layer was made of Pd metal and when the second layer was made of one of Ti, Nb, Mo and W, instead of Pd.
As yet another example, Japanese Patent Application Publication No. 2004-221493 disclosed an electrode to be laminated on the surface of an n-type nitride semiconductor layer, the electrode being provided with, from the bottom, an Ti layer (e.g., 30 nm), an Al layer (e.g., 150 nm), a Mo layer (e.g., 30 nm), a Pt layer (e.g., 15 nm), and a Au layer (e.g., 200 nm) in sequential order, such that delamination of the Au layer is suppressed and diffusion of the Au layer into the semiconductor layer side can be nearly completely suppressed.